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Showing 2 results for Salarifard
Muhammad Rasoul Akhoundi Zardeyni, Raziyeh Salarifard,
Volume 11, Issue 1 (9-2022)
Abstract
Elliptic curve cryptography (ECC) provides the same security with shorter key lengths in comparison with other asymmetric cryptography algorithms. One of the safest curves recently considered is the Edwards25519, which is standardized by NIST. The most expensive operation in the ECC is point multiplication, which uses field multiplication many times. In this paper, a high-speed field multiplication for Edwards25519 is proposed. The improvements are mostly the result of the development of a novel semi-systolic field multiplier which employs four steps of Karatsuba-Ofman multiplication with fewer additions/subtractions in comparison with the original ones. The proposed multiplier has four register layers in its architecture. Then, this architecture, while taking advantage of the systolic architecture (a low CPD), has a low latency. In comparison with the best previous work, the proposed field multiplication has a 28% improvement in speed. Moreover, the point multiplication which exploits the proposed field multiplication has a 50% improvement in time in comparison with the best previous work.
Reza Rashidian, Raziyeh Salarifard , Ali Jahanian,
Volume 12, Issue 2 (2-2024)
Abstract
The adoption of post-quantum encryption algorithms to replace older asymmetric algorithms is of paramount importance. Diverse categories of post-quantum encryption, including lattice-based and code-based cryptography, are currently in the final stages of NIST's standardization competition, with the aim of providing security against quantum computers. Among the lattice-based key encapsulation mechanisms (KEM) garnering attention in this competition, the NTRU Prime algorithm stands out. The primary challenge in implementing such algorithms revolves around executing resource-intensive polynomial multiplications within a ring structure. Leveraging the Number Theoretic Transform (NTT) allows us to achieve polynomial multiplication with near-linear efficiency (O (n log n)). To enhance hardware efficiency, butterfly structures are frequently employed in NTT multipliers. Our research centers on comparing our approach with the best multiplication implementations utilized in NTRU Prime on FPGA up to the present version. This involves the redesign and modification of data preprocessing methods and storage structures, resulting in an increase in frequency and a reduction in the utilization of LUT resources.
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